An electronic circuit arrangement can include a semiconductor chip and a chip carrier, which are at least partly packaged in a housing (so-called packaging). The chip carrier for the at least one semiconductor chip has a plurality of functions in a finished package. It serves as a stable bearing and holding area to which the semiconductor chip is fixedly connected, dissipates heat that arises, and provides the electrical connections for the semiconductor chip. That is to say that it forms the contact elements for the electronic circuit arrangement which are connected to printed circuit boards, for example, in a further processing step.
The semiconductor chip is usually connected to a chip contact location of the chip carrier (so-called die pad). There are various methods for producing the necessary electrical contacts between the chip carrier and the semiconductor chip. In the case of wire bonding, the semiconductor chip is fixed on the chip contact location and connected to the contact elements of the chip carrier by means of fine wires. The chip contact location then often only forms an electrical conducting line for the semiconductor chip. Such wire bonding to a chip carrier is known for example from German patent application DE 100 31 204.
In the case of the flip-chip method, the unhoused semiconductor chip is applied directly to the contact elements of the chip carrier without further wiring. The chip contact location provides a plurality of contact elements with which the chip comes into electrical contact upon application to the chip carrier. The method is more efficient since all the connections are produced in one method step. In the case of very complex circuits, this technology often affords the only practical possibility for connection because hundreds of contacts can be realized. With the flip-chip method, it is possible here to utilize the entire area of the chip contact location for the connections. This is not possible, or is possible only to a very limited extent, in the case of wire bonding because wires would then cross one another and very probably make contact with one another.
In both cases it is important to produce a stable connection having high electrical and thermal conductivity between the chip carrier, specifically between the chip contact location, and the semiconductor chip.
The chip carrier has a substrate that forms its basic framework and is produced from metal, in particular copper, copper alloys, iron-nickel alloys, and other alloys.
For better further processing of the electronic circuit arrangement, the substrate is preferably provided with at least one soldering layer. Tin or SnPb alloys have been customary for this. Both variants have disadvantages, however. Thus, as is known, lead-containing alloys are avoided on account of the high toxicity. Tin-plated chip carriers tend to form so-called whiskers, acicular elongate crystals, which can lead to short circuits when the circuit arrangement is mounted on printed circuit boards. In order to avoid these problems, it is known from Korean patent application KR 2002 094965, for example, to use palladium-containing soldering layers composed of NiPd or NiPdAu alloys.
These soldering layers have the disadvantage, however, that eutectic bonding with metalized chips, for example, by means of an AuSn or AuAs alloy, is not possible. This is particularly problematic since stringent requirements with regard to reliability, stability and also thermal and electrical conductivity are made of the connection of the chip to the chip carrier.
U.S. Pat. No. 6,376,901 B1 discloses a chip carrier (a so-called leadframe) for integrated semiconductor circuits wherein a nickel layer is plated onto the metallic carrier over the whole area and a palladium layer is plated onto the nickel layer, selectively covering bonding locations of the leadframe. Soldering agent is applied to the nickel layer where parts of the circuit arrangement are intended to be applied to the carrier.